MT8791 Embedded system Design MCQ Test
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1)How many clock pulses are confined by each
machine cycle of Peripheral-Interface Controllers? * a.
4 b.
8 c.
12 d.
16 2) Which flags are more likely to get affected
in status registers by Arithmetic and Logical Unit (ALU) of PIC 16 CXX on the
basis of instructions execution? * a.
Carry (C) Flags b.
Zero (Z) Flags c.
Digit Carry (DC) Flags d.
All of the above 3) What is the execution speed of instructions
in PIC especially while operating at the maximum value of clock rate? * a.
0.1 μs b.
0.2 μs c.
0.4 μs d.
0.8 μs 4) Which operational
feature of PIC allows it to reset especially when the power supply drops the
voltage below 4V? * a.
Built-in Power-on-reset b.
Brown-out reset c.
Both a & b d.
None of the above 5) Which among the below stated reasons is/are
responsible for the selection of PIC implementation/design on the basis of
Harvard architecture instead of Von-Newman architecture? * a.
Improvement in bandwidth b.
Instruction fetching becomes possible over a single instruction cycle c.
Independent bus access provision to data memory even while accessing the
program memory d.
All of the above Option
1 6) Which among the below specified major
functionalities is/are associated with the programmable timers of PIC? a.
Excogitation of Inputs b. Handling of Outputs c. Interpretation of internal
timing for program execution d. Provision of OTP for large and small
production runs * a.
Only C b.
C & D c.
A, B & D d.
A, B & C 7) Which timer/s possess an ability to prevent
an endless loop hanging condition of PIC along with its own on-chip RC
oscillator by contributing to its reliable operation? * a.
Power-Up Timer (PWRT) b.
Oscillator Start-Up Timer (OST) c.
Watchdog Timer (WDT) d.
All of the above 8) Which among the CPU registers of PIC
16C6X/7X is not 8-bit wide? * a.
Status Register b.
Program Counter Latch (PCLATH) Register c.
Program Counter Low Byte (PCL) Register d.
File Selection Register (FSR) 9) Which register/s is/are mandatory to get loaded
at the beginning before loading or transferring the contents to corresponding
destination registers? * a.
W b.
INDF c.
PCL d.
All of the above 10) How many RPO status bits are required for
the selection of two register banks? * a.
1 b.
2 c.
8 d.
16 11) The RPO status
register bit has the potential to determine the effective address
of______ * a.
Direct Addressing Mode b.
Indirect Addressing Mode c.
Immediate Addressing Mode d.
Indc. Watchdog Timer (WDT) exed Addressing Mode 12) Which status bits
exhibit carry from lower 4 bits during 8-bit addition and are especially
beneficial for BCD addition? * a.
Carry bit (C) b.
Digits Carry bit (DC) c.
Both a & b d.
None of the above 13) Which statement is precise in relation to
FSR, INDF and indirect addressing mode? a. Address byte must be written in
FSR before executing INDF instruction in indirect addressing mode b. Address
byte must be written in FSR after executing INDF instruction in indirect
addressing mode c. Address byte must be written in FSR at the same time
during the execution of INDF instruction in indirect addressing mode d.
Address byte must be always written in FSR as it is independent of any
instruction in indirect addressing mode * a.
Only A b.
Only B c.
Only A & B d.
A & D 14) Which among the below stated registers
specify the address reachability within 7 bits of address independent of RP0
status bit register? * a.
PCL b.
FSR c.
INTCON d.
All of the above 15) Where do the contents of PCLATH get
transferred in the higher location of program counter while writing in PCL
(Program Counter Latch)? * a.
11th bit b.
12th bit c.
13th bit d.
14th bit 16) Which condition/s of MCLR (master clear)
pin allow to reset the PIC? * a.
High b.
Low c.
Moderate d.
All of the above Option
2 17) Generation of Power-on-reset pulse can
occur only after __________ * a.
the detection of increment in VDD from 1.5 V to 2.1 V b.
the detection of decrement in VDD from 2.1 V to 1.5 V c.
the detection of variable time delay on power up mode d.
the detection of current limiting factor 18) What is the rate of power up delay
provided by an oscillator start-up timer while operating at XT, LP and HS
oscillator modes? * a.
512 cycles b.
1024 cycles o c.
2048 cycles o d.
4096 cycles 19) Which kind of mode is favourable for MCLR
pin for indulging in reset operations? * o a.
Normal mode o b.
Sleep mode o c.
Power-down mode o d.
Any flexible mode 20) What is the purpose of using the start-up
timers in an oscillator circuit of PIC? * o a.
For ensuring the inception and stabilization of an oscillator in a proper
manner o b.
For detecting the rise in VDD o c.
For enabling or disabling the power-up timers o d.
For generating the fixed delay of 72ms on power-up timers 21) Which program location is allocated to the
program counter by the reset function in Power-on-Reset (POR) action
modes? * o a.
Initial address o b.
Middle address o c.
Final address o d.
At any address reliable for reset operations 22) When does it become very essential to use
the external RC components for the reset circuits? * o a.
Only if initialization is necessary for RAM locations o b.
Only if VDD power-up slope is insufficient at a requisite level o c.
Only if voltage drop exceeds beyond the limit o d.
Only if current limiting factor increases rapidly 23) Which among the below mentioned PICs do
not support the Brown-Out-Reset (BOR) feature? a. PIC 16C66 B. PIC 16C74 C.
PIC 16C61 D. PIC 16C71 * o a.
A & B o b.
C & D o c.
A & C o d.
B & D 24) Which crucial feature/function of
Brown-Out-Reset (BOR) makes the PIC to be completely unique and distinct from
other microcontrollers? * o a.
It can reset the PIC automatically in running condition o b.
It can reset the PIC even when the supply voltage increases above 4V o c.
It can reset the PIC without enabling the power-up timer o d.
All of the above 25) What happens when the supply voltage falls
below 4V during the power-up timer delay of 72ms in PIC? * o a.
CPU resets PIC once again in BOR mode o b.
BOR reset mode gets disabled o c.
PIC does not remain in BOR mode until the voltage increases irrespective of
stability o d.
Power-up timer kills 72ms more again 26) What output is generated by OSC2 pin in
PIC oscillator comprising RC components for sychronizing the peripherals with
PIC microcontroller? * o a.
(1/2) x frequency of OSC1 o b.
(1/4) x frequency of OSC1 o c.
(1/8) x frequency of OSC1 o d.
(1/16) x frequency of OSC1 27) Which form of clocking mechanism is highly
efficient and reliable for crystal or ceramic clock sources for operating at
the range of 5- 200 kHz in PIC? * o a.
RC o b.
LP (Low-Power Clocking) o c.
XT o d.
HS (High Speed) 28) Which significant feature/s of crystal
source contribute/s to its maximum predilection and utility as compared to
other clock sources? * o a.
High accuracy o b.
Proficiency in time generation o c.
Applicability in real-time operations o d.
All of the above 29) What is the executable frequency range of
High speed (HS) clocking method by using cystal/ ceramic/ resonator or any
other external clock source? * o a.
0-4 MHz o b.
5-200 KHz o c.
100kHz- 4 MHZ o d.
4-20 MHz 30) How many bits are required for addressing
2K & 4K program memories of PIC 16C61 respectively? * o a.
4 & 8 bits o b.
8 & 16 bits o c.
11 & 12 bits o d.
12 & 16 bits 31) What location is attributed to ‘goto
Mainline’ instruction in the program memory of PIC 16C61? * o a.
000H o b.
004H o c.
001H o d.
011H 32) When do the special address 004H get
automatically loaded into the program counter? * o a.
After the execution of RESET action in program counter o b.
After the execution of ‘goto Mainline ‘ instruction in the program memory o c.
At the occurrence of interrupt into the program counter o d.
At the clearance of program counter with no value 33) How many bits are utilized by the
instruction of direct addressing mode in order to address the register files
in PIC? * o a.
2 o b.
5 o c.
7 o d.
8 34) Which registers are adopted by CPU and
peripheral modules so as to control and handle the operation of device
inhibited in RFS? * o a.
General Purpose Register o b.
Special Purpose Register o c.
Special Function Registers o d.
All of the above 35) Which among the below specified registors
are addressable only from bank1 of RFS? * o a.
PORTA (05H) o b.
PORTB (06H) o c.
FSR (04H) o d.
ADCON0 (07H) 36) Which register acts as an input-output
control as well as data direction register for PORTA in bank 2 of RFS? * o a.
INDF (80H) o b.
TRISB (85H) o c.
TRISA (85H) o d.
PCLATH (8A) 37) Which bank of RFS has a provision of
addressing the status register? * o a.
Only Bank 1 o b.
Only Bank 2 o c.
Either Bank 1 or Bank 2 o d.
Neither Bank 1 nor Bank 2 38) Which bit of OPTION register has a
potential to decide the falling or rising edge sensitivity for the external
interrupt INT? * o a.
RBPU o b.
INTEDG o c.
PSA o d.
RTS 39) Where are the prescalar assignments
applied with a usage of PSA bit? * o a.
Only RTCC o b.
Only Watchdog timer o c.
Either RTCC or Watchdog timer o d.
Neither RTCC nor Watchdog timer 40) Where is the exact specified location of
an interrupt flag associated with analog-to-digital converter? * o a.
INTCON o b.
ADCON0 o c.
ADRES o d.
PCLATH 41) Which bit permits to enable (if set) or
disable (if cleared) all the interrupts in an INTCON register? * o a.
GIE o b.
ADIE o c.
RBIE o d.
TOIE 42) When does it become possible for a bit to
get accessed from bank ‘0’ in the direct addressing mode of PICs? * o a.
Only when RPO bit is set ‘zero’ o b.
Only when RPO bit is set ‘1’ o c.
Only when RPO bit is utilized along with 7 lower bits of instruction code o d.
Cannot Predict 43) When does it become feasible for portB
pins (RB4 to RB7) to support its unique feature of ‘interrupt on
change’? * o a.
By configuring all the pins (RB4-RB7) as inputs o b.
By configuring all the pins (RB4-RB7) as outputs o c.
By configuring any one of the pins as inputs o d.
By configuring any one of the pins as outputs 44) Which digital operations are performed
over the detected mismatch outputs with an intention to generate a single
output RB port change output? * o a.
OR o b.
AND o c.
EX-OR o d.
NAND 45) What is the purpose of acquiring two
different bits from INTCON register for performing any interrupt operation in
PIC 16C61 / 71? * o a.
One for enabling & one for disabling the interrupt o b.
One for enabling the interrupt & one for its occurrence detection o c.
One for setting or clearing the RBIE bit o d.
None of the above |
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